In recent years, application programs have been expanded rapidly in capacity to cope with required processings, typically those of enhanced cellular phones and accordingly, conventional NOR type flash memories have come to be insufficient to meet such required capacities. And instead of those NOR type flash memories, the use of memory modules has been proposed to solve the problem. A memory module, as disclosed in JP-A-2002-366429 and JP-A-2003-091463, consists of a NAND type flash memory, as well as a control circuit that incorporates an SRAM. The NAND type flash memory provides one bit line contact for a unit of 16 to 128 cells, so that the area of one bit memory cell can be smaller than that of the NOR type flash memory. This is why the NAND type flash memory can satisfy the requirement of a larger capacity while its read time required to output the first data is as slow as about 25 μs to 50 μs.
Each of the memory modules disclosed in JP-A-2002-366429 and JP-A-2003-091463 incorporates a RAM and a NAND type flash memory. The memory module realizes a read time of about 80 to 200 ns by transferring data to the RAM from the NAND type flash memory beforehand, then by reading the data from the RAM.
Particularly, according to the technique disclosed in each of JP-A-2002-366429 and JP-A-2003-091463, when transferring data to the RAM from the NAND type flash memory beforehand, the CPU issues a write command to the control circuit, thereby the transfer address and the transfer size are written to a control register provided in the control circuit. The write command instructs the control circuit to write the necessary transfer address and transfer size to the control register.